In addition to caches and prefetchers, a processor may employ a branch predictor to reduce instruction execution latency. The branch predictor may be a digital circuit that tries to guess which way a branch (e.g., an if-then-else structure) will go before known definitively. Additionally, or alternatively, the branch predictor may attempt to guess whether a conditional jump will be taken or not and/or guess a target of a taken conditional or unconditional jump before the target has been computed, for example, by decoding and executing the instruction itself.